Logic Level MOS Field Effect Transistor

NTE
Type
Number
Description
and
Application
Case
Style
Drain to
Source
Breakdown
Voltage
(Volts)
Gate to
Source
Cutoff
Voltage
(Volts)
Gate to
Source
Breakdown
Voltage
(Volts)
Maximum
Continuous
Drain
Current
(Amps)
Static
Drain to
on Source
Resistance
(Ohms)
Input
Capacitance
(pf)
Forward
Transcon-
ductance
(mhos)
Device
Total Power
Dissipation
@TC=25°C
(Watts)
BVDSS Vgs(Off) BVGSS ID rDS(On) Ciss gfs PD
2980 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO251 60 Min 2.0 Max ±10 Max 7.7 0.20 Max 400 Typ 3.4 Min 25 Max
td(off) = 17ns, td(on) = 9.3ns,tf = 26ns, tr = 110ns
2981 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO251 100 Min 2.0 Max ±10 Max 7.7 0.27 Max 490 Typ 4.4 Min 42 Max
td(off) = 21ns, td(on) = 9.8ns,tf = 27ns, tr = 64ns
2984 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO220 60 Min 2.0 Max ±10 Max 17 0.10 Max 8700 Typ 7.33 Min 60 Max
td(off) = 23ns, td(on) = 11ns,tf = 41ns, tr = 110ns
2985 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO220 60 Min 2.0 Max ±10 Max 30 0.05 Max 1600 Typ 12 Min 88 Max
td(off) = 30ns, td(on) = 14ns,tf = 56ns, tr = 170ns
2986 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO220 60 Min 2.0 Max ±10 Max 50 0.028 Max 3300 Typ 23 Min 150 Max
td(off) = 42ns, td(on) = 17ns,tf = 110ns, tr = 230ns
2987 N-CHANNEL
Enhancement
Mode High
Speed Switch
TO220 100 Min 2.5 Max ±15 Max 20 0.12 Max 1200 Typ 10 Min 105 Max
td(off) = 80ns, td(on) = 50ns,tf = 80ns, tr = 140ns
DESCRIPTION
The NTE series Logic Level MOSFETs are compatible with the 5-volt power-supply requirement of logic circuitry. These devices do not require an interface circuit between it and the CMOS logic driver; therefore, the extra cost of the interface circuit power supply is eliminated.

The chief physical structural difference between Logic Level and other MOSFETs, and the electrical reason for its difference in performance, is its gate insulation thickness, which has been reduced from 100nm industry standard to 50nm (500 angstroms), yet which retains the dynamic strength to handle the high voltage applied to power transistors. Since the surface inversion of the MOS channel is determined by the gate-insulator voltage field, the halving of the gate-oxide thickness should be expected to have a major effect on the gate voltage required. In fact, this reduction is the reason for voltage reduction from 10 volts (standard MOSFETs) to 5 volts (Logic Level MOSFETs).

Tight control of the temperature vs. time and oxygen vs. time profiles applied to the silicon substrate during oxide growth assures consistant preformance through the development of good transition regions between the oxide, the silicon below it, and thew polysilicon above it. The reduction in gate insulator thickness makes possible easy ON/OFF control of the Logic Level MOSFETs by CMOS logic alone, and by microprocessors.





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